Apacer Technology Pinpoints Accuracy with 3D NAND Flash Optimization, Searching for the Ideal Balance between Cost and Performance

Oct 29, 2019

NAND Flash has become a mature technology, and the varieties of formats that are now available are already adopted in many industrial applications. However, with the desire to go beyond the standard options, Apacer has developed certain optimizations of NAND Flash technology. The goal of these optimizations is to provide customers with the amount of P/E cycles that best suits their application.

Previously, Apacer developed one form of NAND Flash optimization known as SLC-lite. The central concept behind SLC-lite is to make 2D MLC behave like SLC. MLC contains two bits, but by programming only one of the two bits, the least significant bit (LSB), the cell distribution behaves almost identically to that of SLC flash. The endurance is then greatly increased, reaching 20,000 P/E cycles. Standard 2D MLC can only reach 3,000 P/E cycles.

However, with the maturity of 3D NAND Flash technology, Apacer’s engineers developed a similar process to SLC-lite for 3D NAND drives. The two new forms of this technology are called SLC-liteX and MLC-liteX. SLC-liteX is based on 3D NAND technology. The firmware is carefully tweaked by Apacer’s engineering team so as to offer the greatest number of P/E cycles in this format – 30,000, which is 10 times more than MLC or industrial 3D TLC. The longest lifespans are therefore available at reasonable cost.

MLC-liteX is also based on 3D NAND technology. The firmware is fine-tuned in such a way as to offer more than three times as many P/E cycles (10,000) than MLC or industrial 3D TLC. Cost-benefit optimization is achieved while lifespans are still extended.

The standard bit format for 3D NAND TLC stores three bits in one cell. MLC-liteX programs only two of the three bits. So the capacity of MLC-liteX is only reduced by a third. The advantage of this tradeoff is that P/E cycles are increased. Continuing in this vein, SLC-liteX programs only one of the three bits. The capacity is therefore reduced by two-thirds, but even more P/E cycles are available.